Samsung is now mass producing the industry's first 3-bit-per cell, 64Gbit NAND flash chip, which uses circuitry that's about 14% smaller than before. The new chips pack twice as many bits as Samsung's current NAND flash offering.
The NAND flash also offers better performance by applying Toggle DDR (Double Data Rate) 1.0 specifications to the new chips. Samsung had been producing 30nm-class NAND chips using SDR (Single Data Rate)-based specifications.
The company claimed it is the first to begin production the new class of flash memory using 20 nanometer (nm) class circuitry. The flash chips will be used to create high-capacity USB flash drives, SD memory cards, as well as smart phones and solid-state drives (SSDs).
Until this year, multi-level cell (MLC) NAND flash enabled up to 2-bits of data to be written to a memory cell. Single-level cell (SLC) NAND has always been considered " enterprise -class" quality because of its higher native life expectancy and performance. However, more sophisticated wear-leveling software in drive controllers has enabled MLC memory to be used in higher-end products.
In August, IM Flash Technologies (IMFT) - a joint venture between Intel and Micron - also announced it had created a 3-bit-per-cell NAND flash chip using 25nm lithography, as the process of laying down circuitry is called. IMFT's chip also holds 64Gbits. IMFT, however, has yet to begin mass production.
According to a slide leaked to the press, Intel expects to eventually double the capacity of its consumer-class SSDs utilizing the 25nm process. That means its X25-M SSDs will grow to 160GB, 300GB and 600GB capacities. The company would also be able to double the capacity of its more affordable X25-V entry-level drive, which is targeted at the netbook and tablet market. The current X25-V offers 40GB capacity. That would be replaced with an 80GB model.
Samsung would not reveal the exact size of its lithography technology, saying only that it is somewhere between 20nm and 29nm in size. Since November, Samsung has been using 30nm lithography technology to develop NAND flash chips with 32Gbit capacity.
At 25nm, the NAND flash circuitry is 3000 times thinner than a strand of human hair.
The new, denser NAND technology makes it possible to build products using fewer chips, allowing for smaller, higher-density designs. The 64Gbit chips are combined to create 8GB NAND flash dies. The dies are then combined to create larger multi-chip products. The change also cuts the overall cost to produce mobile products, savings that can be passed down to consumers .
"By now entering into full production of 20nm-class, 64Gbit, 3-bit devices, we expect to accelerate adoption of our high-performance NAND solutions that use Toggle DDR technology, for applications that also require high-density NAND," Seijin Kim, vice president of Flash Memory Planning/Enabling at Samsung Electronics, said in a statement.
Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at @lucasmearian or subscribe to Lucas's RSS feed . His e-mail address is email@example.com .
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