Rice University announced today that scientists there have created the first two-terminal memory chips that use only silicon, extending the limits of miniaturization subject to Moore's Law.
The new technology places multiple layers of memory capacity on the same chip, creating what is referred to as a 3-D memory architecture.
According to a Rice University spokesman, the new memory technology will improve scalability by an order of magnitude compared to NAND flash technology available today. "The fact that they can do this in 3D makes makes it highly scalable," he said. "We've got memory that's made out of dirt-cheap material and it works."
In 2008, researchers at the university showed how electrical currents could repeatedly break and reconnect 10-nanometer strips of graphite, which could potentially boost flash memory capacity by many times. The Rice researchers said then that the new technology could withstand radiation and temperatures of 200 degrees Celsius that would cause solid-state disk memory to disintegrate.
At the time, the research team acknowledged that they weren't sure why their discovery worked so well. With the latest finding, the research team, including professors James Tour, Douglas Natelson and Lin Zhong, proved the circuit doesn't need the carbon to function, only silicon.
During the project, Jun Yao, a graduate student in Tour's lab, was able to confirm the hypothesis when he sandwiched an insulating layer of silicon oxide between semiconducting sheets of polycrystalline silicon that served as the top and bottom electrodes, Rice said.
Yao applied a charge to the electrodes, which created a conductive pathway by stripping oxygen atoms from the silicon oxide, forming a chain of nanometer-sized silicon crystals. Once formed, the chain can be repeatedly broken and reconnected by applying a pulse of varying voltage, the University said.
"It is more than 5 times denser than 20 nanometer flash ... without 3D stacking," Zhong said. "I would argue the nanowire-based solution is much more amenable to vertical stacking, which makes the technology very scalable as process technology improves. The density can be further doubled or tripled with two or three layers."
Unlike NAND flash memory, which is controlled by three terminals or wires, the new silicon memory requires two terminals, making it more viable for three-dimensional or stacked silicon arrays -- multiplying a chip's capacity. But like flash memory, chips made with silicon consume virtually no power while keeping data intact.
The nanocrystal wires are as small as 5 nanometers wide. A nanometer is one billionth of a meter.
"The beauty of it is its simplicity," said Tour, a professor of mechanical engineering and materials science and computer science, in a statement.
Because the layers of silicon-oxide memory are not required to hold a charge, they can also be stacked one atop another, he added.
"I've been told by industry that if you're not in the 3-D memory business in four years, you're not going to be in the memory business. This is perfectly suited for that," Tour said.
"Manufacturers feel they can get pathways down to 10 nanometers. Flash memory is going to hit a brick wall at about 20 nanometers ," Tour said. "But how do we get beyond that? Well, our technique is perfectly suited for sub-10-nanometer circuits."
PrivaTran, a tech design company based in Austin, is already testing a silicon-oxide chip with 1,000 memory elements built in collaboration with Tour's lab.
"We're real excited about where the data is going here," said PrivaTran CEO Glenn Mortland, who is using the technology in several projects supported by the Army Research Office, National Science Foundation, Air Force Office of Scientific Research, and the Navy Space and Naval Warfare Systems Command Small Business Innovation Research (SBIR) and Small Business Technology Transfer programs.
"Our original customer funding was geared toward more high-density memories," Mortland said. "That's where most of the paying customers see this going. I think, along the way, there will be side applications in various nonvolatile configurations."
NuPGA, a company formed last year through collaborative patents with Rice University, is also demonstrating how silicon oxide also works in reprogrammable gate arrays. NuPGA's devices will assist in the design of computer circuitry based on vertical arrays of silicon oxide embedded in "vias," the holes in integrated circuits that connect layers of circuitry.
Such rewritable gate arrays could drastically cut the cost of designing complex electronic devices, according to Tour.
Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at @lucasmearian , or subscribe to Lucas's RSS feed . His e-mail address is email@example.com .
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